What is static memory allocation

Dynamic memory

DRAM: Dynamic Random Access Memory

Dynamic memory with random access. This type of memory is generally used as main memory. Dynamic memories are characterized by the storage of information in a capacitor, which, like a battery, can absorb energy and hold it for a certain period of time. If, for example, a logical one is to be stored, this capacitor is charged, and discharged with a logical zero. These capacitors are arranged in a matrix of rows and columns.

In order to keep the chips mechanically small and to save connections and thus costs, the electrical control of these components takes place in two stages: The address of a datum is divided into a row address and a column address according to the matrix. ) Address that are transmitted one after the other via the same connections on the chip.

The advantage of this technology is that it can be produced relatively inexpensively and with high densities. The disadvantage is that this capacitor cannot be produced ideally - again similar to a battery that is not used for a long time, this capacitor discharges. To prevent the data from becoming unusable, it must be refreshed at regular intervals.

There are several advancements to this basic architecture that should be briefly touched upon:

FPM: Fast Page Mode
Memory modules with Fast Page Mode are a further development of the "standard" DRAM memory, which, thanks to a special control option, accelerates the technology-related delay times in certain applications.

Most of the time, related memory contents are processed by the processor within computer programs. When a memory bank is accessed, the row address and then the column address are normally transferred first. In the case of successive memory addresses, on the other hand, only the column address changes because the successive data are in the same row (in the same "page"); so that a renewed transmission of the unchanged row address is actually unnecessary. Fast Page Mode makes use of this fact. The row and column addresses are only transferred on the first access, and only the column addresses on subsequent accesses, so that the cycle time until the data is available at the outputs of the memory bank is shortened. This mode must of course be supported by the system used and its chipset.

EDO: Extended Data Output
Memory modules with EDO, in turn, represent a further development compared to FPM memories, where memory access is also accelerated by certain control technologies.

With FPM memories, the electrical signal of the data lines is deleted (not to be confused with the content of the memory cell; this is retained!) When new address information is created. Since the further processing of the data also takes a certain period of time, there is a period of time when the memory has to be "kept still" so that the electrical signals applied to the data lines can be recorded and further processed. In the case of EDO memories, the output stage is designed in such a way that pending information is retained even if a new address is transmitted. In this way, the pending data word can be processed simultaneously and the next requested address can be loaded into the memory module. This also shortens the cycle times.

SDRAM: Synchronous Dynamic Random Access Memory
Similar to FPM and EDO, SDRAM technology is merely a further development of existing memory architectures or their access modes. Unlike FPM or EDO, however, SDRAM technology is not backwards compatible, ie SDRAM memories can only be used in computer systems that also expressly support this technology.

The further development of SDRAM is nothing more than the relocation of part of the memory controller to the memory chip. This step is roughly comparable to the introduction of IDE hard disks, which also have the controller tailored to your special needs built into the housing.

Like the FPM or EDO types of access, the SDRAM technology can show its strengths with consecutive data in the address space. As with all DRAM types, typical SDRAM access takes place with the successive transmission of the row and column addresses. In contrast to previous technologies, a "command transmission" to the SDRAM also takes place during this addressing, with defined processes being set in motion on the memory chip depending on the command.

A typical command could, for example, be: Read out address X and the three subsequent addresses.

In this case, the value for the start address X is transmitted together with the command, and the contents of the four consecutive addresses are transmitted without further action. Since the point in time at which the requested data must be valid, SDRAM modules are supplied with a clock signal with which all processes are synchronized.
The use of SDRAM memories brings speed advantages when large amounts of data have to be transferred in blocks, e.g. with large graphics.